1. Technical Field
The subject matter described herein relates to systems, apparatuses, and methods for compliant dielectric layers for semiconductor devices.
2. Background Art
An integrated circuit (IC) is a common element of electronic devices. An IC typically includes a die (or chip), upon which electrical circuits are formed, and a package that houses the die. Various types of IC packages currently exist. For instance, wafer level packages exist that are basically dies cut from wafers that have interconnects (e.g., solder bumps) mounted directly thereto. The solder bumps are spaced out on the dies by redistribution layers (RDLs) to enable the solder bumps to be directly mounted. The solder bumps enable the wafer level packages to be mounted to circuit boards and the like. Another type of IC package includes an interposer to which an IC die is mounted. Such a package may be considered another type of wafer level package. The interposer is made of a semiconductor material (e.g., silicon) and includes electrically conductive routing and vias, such as through silicon vias (TSVs), and may be referred to as a through silicon via interposer (TSI). The electrically conductive routing traces and vias of the interposer are used to spread out and route signals of the IC die, which is attached to a first surface of the interposer, to interconnects (e.g., solder bumps) on the second, opposing surface of the interposer. The interconnects are used to mount the interposer-enabled package to a circuit board.
During the manufacturing process, such packages undergo temperature cycles (e.g., heating and cooling), which causes thermal expansion of the semiconductor material of the die in a wafer level package, and of the die and interposer in an interposer-enabled wafer level package. Such expansion, or enlarging of the area of the die or interposer, can cause mechanical stress on the semiconductor material and/or on a passivation layer on the semiconductor material and/or on solder bumps/balls and/or on under bump metallization (UBM) layers (i.e., layers that interface a solder ball/bump with the semiconductor material terminals). This is because the semiconductor material may expand at different rates from other materials, including substrate material of a circuit board to which the package is mounted. This difference in thermal expansion rates (due to differences in values of coefficients of thermal expansion—CTEs) can cause cracking, delamination, circuit damage, etc. Furthermore, the larger the die or interposer, the larger the problem becomes, causing a limitation in sizes of dies and interposers that may be used. For instance, current silicon interposer sizes are limited to approximately 600 mm2 (e.g., 25.5 mm×23.6 mm)